Method of manufacturing semiconductor package having connection structure with tapering connection via layers

ABSTRACT

A semiconductor package includes: a connection structure having first and second surface opposing each other and including a plurality of insulating layers, a plurality of redistribution layers, and a plurality of connection vias; at least one semiconductor chip on the first surface having connection pads electrically connected to the plurality of redistribution layers; an encapsulant on the first surface encapsulating the at least one semiconductor chip; and UBM layers including UBM pads on the second surface and UBM vias connecting a redistribution layer. At least one connection via adjacent to the first surface has a tapered structure narrowed toward the second surface, and the other connection vias and the UBM vias have a tapered structure narrowed toward the first surface.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.16/571,723, filed Sep. 16, 2019, which claims benefit of priority toKorean Patent Application No. 10-2018-0117697 filed on Oct. 2, 2018 inthe Korean Intellectual Property Office, the disclosures of which areincorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package.

BACKGROUND

In accordance with improvement of specifications of a set and use of ahigh bandwidth memory (HBM), the interposer market has grown. Currently,silicon is been mainly used as a material of interposers, butdevelopment of a glass or organic method has been conducted in order toincrease an area and reduce costs.

Meanwhile, an interposer package is manufactured by performing a packageprocess of attaching a die to the interposer and molding the die, and aconnection structure that is to be used as an interposer and has aredistribution layer is manufactured before a semiconductor chip ismounted. However, in a build-up process of the redistribution layers forsuch a connection structure, undulation may severely occur.Particularly, it is difficult to maintain a critical dimension of aredistribution layer to be formed subsequently. Resultantly, reliabilityof the package may be significantly decreased.

SUMMARY

An aspect of the present disclosure may provide a semiconductor packagein which an undulation problem occurring in a build-up process of aconnection structure may be solved.

According to an aspect of the present disclosure, a semiconductorpackage may include: a connection structure having first and secondsurface opposing each other and including a plurality of insulatinglayers, a plurality of redistribution layers disposed on the pluralityof insulating layers, respectively, and a plurality of connection viaspenetrating through the plurality of insulating layers and connected tothe plurality of redistribution layers, respectively; at least onesemiconductor chip disposed on the first surface of the connectionstructure and having connection pads electrically connected to theplurality of redistribution layers; an encapsulant disposed on the firstsurface of the connection structure and encapsulating the at least onesemiconductor chip; and underbump metallurgy (UBM) layers including UBMpads disposed on the second surface of the connection structure and UBMvias connecting the UBM pads and a redistribution layer adjacent to thesecond surface of the connection structure among the plurality ofredistribution layers to each other. At least one connection viaadjacent to the first surface among the plurality of connection vias mayhave a tapered structure narrowed toward the second surface, and theother connection vias of the plurality of connection vias and the UBMvias may have a tapered structure narrowed toward the first surface.

According to another aspect of the present disclosure, a semiconductorpackage may include: a connection structure having first and secondsurface opposing each other and including a plurality of insulatinglayers, a plurality of redistribution layers disposed on the pluralityof insulating layers, respectively, and a plurality of connection viaspenetrating through the plurality of insulating layers and connected tothe plurality of redistribution layers, respectively; at least onesemiconductor chip disposed on the first surface of the connectionstructure and having connection pads electrically connected to theplurality of redistribution layers; an encapsulant disposed on the firstsurface of the connection structure and encapsulating the at least onesemiconductor chip; UBM layers disposed on the second surface of theconnection structure and electrically connected to the plurality ofredistribution layers; and a passivation layer disposed on the secondsurface of the connection structure and embedding at least portions ofthe UBM layers. The plurality of insulating layers may include the sameinsulating material, at least one connection via adjacent to the firstsurface among the plurality of connection vias may have a taperedstructure narrowed toward the second surface, and the other connectionvias of the plurality of connection vias may have a tapered structurenarrowed toward the first surface.

According to another aspect of the present disclosure, a semiconductorpackage may include: a connection structure including insulating layers,redistribution layers disposed on the insulating layers, respectively,and connection via layers penetrating through the insulating layers andconnected to the redistribution layers, respectively; and asemiconductor chip disposed on the connection structure and havingconnection pads electrically connected to the redistribution layers. Afirst connection via layer among the connection via layers and a secondconnection via layer among the connection via layers may be tapered inopposite directions.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the presentdisclosure will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a schematic block diagram illustrating an example of anelectronic device system;

FIG. 2 is a schematic perspective view illustrating an example of anelectronic device;

FIG. 3 is a schematic cross-sectional view illustrating a case in whicha three-dimensional (3D) ball grid array (BGA) package is mounted on amain board of an electronic device;

FIG. 4 is a schematic cross-sectional view illustrating a case in whicha 2.5D silicon interposer package is mounted on a main board;

FIG. 5 is a schematic cross-sectional view illustrating a case in whicha 2.5D organic interposer package is mounted on a main board;

FIG. 6 is a schematic cross-sectional view illustrating a semiconductorpackage according to an exemplary embodiment in the present disclosure;

FIG. 7 is a plan view taken along line I-I′ of the semiconductor packageof FIG. 6 ;

FIG. 8 is an enlarged cross-sectional view of portion “A” of thesemiconductor package of FIG. 6 ;

FIGS. 9A through 9F are cross-sectional views for describing mainprocesses of manufacturing a connection structure in a method ofmanufacturing the semiconductor package illustrated in FIG. 6 ;

FIGS. 10A through 10C are cross-sectional views for describing mainprocesses of mounting a semiconductor chip in the method ofmanufacturing the semiconductor package illustrated in FIG. 6 ;

FIG. 11 is a schematic cross-sectional view illustrating a semiconductorpackage according to another exemplary embodiment in the presentdisclosure; and

FIG. 12 is a plan view taken along line II-IF of the semiconductorpackage of FIG. 11 .

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will bedescribed with reference to the accompanying drawings. In theaccompanying drawings, shapes, sizes, and the like, of components may beexaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like,are used to refer to a downward direction in relation to cross sectionsof the drawings for convenience, while an upper side, an upper portion,an upper surface, and the like, are used to refer to an oppositedirection to the downward direction. However, these directions aredefined for convenience of explanation, and the claims are notparticularly limited by the directions defined as described above, andconcepts of upper and lower portions may be exchanged with each other.

The meaning of a “connection” of a component to another component in thedescription conceptually includes an indirect connection through anadhesive layer as well as a direct connection between two components. Inaddition, “electrically connected” conceptually includes a physicalconnection and a physical disconnection. It can be understood that whenan element is referred to with terms such as “first” and “second”, theelement is not limited thereby. They may be used only for a purpose ofdistinguishing the element from the other elements, and may not limitthe sequence or importance of the elements. In some cases, a firstelement may be referred to as a second element without departing fromthe scope of the claims set forth herein. Similarly, a second elementmay also be referred to as a first element.

The term “an exemplary embodiment” used herein does not refer to thesame exemplary embodiment, and is provided to emphasize a particularfeature or characteristic different from that of another exemplaryembodiment. However, exemplary embodiments provided herein areconsidered to be able to be implemented by being combined in whole or inpart one with one another. For example, one element described in aparticular exemplary embodiment, even if it is not described in anotherexemplary embodiment, may be understood as a description related toanother exemplary embodiment, unless an opposite or contradictorydescription is provided therein.

Terms used herein are used only in order to describe an exemplaryembodiment rather than limiting the present disclosure. In this case,singular forms include plural forms unless interpreted otherwise incontext.

Electronic Device

FIG. 1 is a schematic block diagram illustrating an example of anelectronic device system.

Referring to FIG. 1 , an electronic device 1000 may accommodate amainboard 1010 therein. The mainboard 1010 may include chip relatedcomponents 1020, network related components 1030, other components 1040,and the like, physically or electrically connected thereto. Thesecomponents may be connected to others to be described below to formvarious signal lines 1090.

The chip related components 1020 may include a memory chip such as avolatile memory (for example, a dynamic random access memory (DRAM)), anon-volatile memory (for example, a read only memory (ROM)), a flashmemory, or the like; an application processor chip such as a centralprocessor (for example, a central processing unit (CPU)), a graphicsprocessor (for example, a graphics processing unit (GPU)), a digitalsignal processor, a cryptographic processor, a microprocessor, amicrocontroller, or the like; and a logic chip such as ananalog-to-digital (ADC) converter, an application-specific integratedcircuit (ASIC), or the like. However, the chip related components 1020are not limited thereto, but may also include other types of chiprelated components. In addition, the chip related components 1020 may becombined with each other.

The network related components 1030 may include protocols such aswireless fidelity (Wi-Fi) (Institute of Electrical And ElectronicsEngineers (IEEE) 802.11 family, or the like), worldwide interoperabilityfor microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE802.20, long term evolution (LTE), evolution data only (Ev-DO), highspeed packet access+(HSPA+), high speed downlink packet access+(HSDPA+),high speed uplink packet access+(HSUPA+), enhanced data GSM environment(EDGE), global system for mobile communications (GSM), globalpositioning system (GPS), general packet radio service (GPRS), codedivision multiple access (CDMA), time division multiple access (TDMA),digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G,and 5G protocols, and any other wireless and wired protocols, designatedafter the abovementioned protocols. However, the network relatedcomponents 1030 are not limited thereto, but may also include a varietyof other wireless or wired standards or protocols. In addition, thenetwork related components 1030 may be combined with each other,together with the chip related components 1020 described above.

Other components 1040 may include a high frequency inductor, a ferriteinductor, a power inductor, ferrite beads, a low temperature co-firedceramic (LTCC), an electromagnetic interference (EMI) filter, amultilayer ceramic capacitor (MLCC), or the like. However, othercomponents 1040 are not limited thereto, but may also include passivecomponents used for various other purposes, or the like. In addition,other components 1040 may be combined with each other, together with thechip related components 1020 or the network related components 1030described above.

Depending on a type of the electronic device 1000, the electronic device1000 may include other components that may or may not be physically orelectrically connected to the mainboard 1010. These other components mayinclude, for example, a camera 1050, an antenna 1060, a display 1070, abattery 1080, an audio codec (not illustrated), a video codec (notillustrated), a power amplifier (not illustrated), a compass (notillustrated), an accelerometer (not illustrated), a gyroscope (notillustrated), a speaker (not illustrated), a mass storage unit (forexample, a hard disk drive) (not illustrated), a compact disk (CD) drive(not illustrated), a digital versatile disk (DVD) drive (notillustrated), or the like. However, these other components are notlimited thereto, but may also include other components used for variouspurposes depending on a type of electronic device 1000, or the like.

The electronic device 1000 may be a smartphone, a personal digitalassistant (PDA), a digital video camera, a digital still camera, anetwork system, a computer, a monitor, a tablet PC, a laptop PC, anetbook PC, a television, a video game machine, a smartwatch, anautomotive component, or the like. However, the electronic device 1000is not limited thereto, but may be any other electronic deviceprocessing data.

FIG. 2 is a schematic perspective view illustrating an example of anelectronic device.

Referring to FIG. 2 , a semiconductor device may be used for variouspurposes in the various electronic devices 1000 as described above. Forexample, a motherboard 1110 may be accommodated in a body 1101 of asmartphone 1100, and various electronic components 1120 may bephysically or electrically connected to the motherboard 1110. Inaddition, other components that may or may not be physically orelectrically connected to the motherboard 1110, such as a camera module1130, may be accommodated in the body 1101. Some of the electroniccomponents 1120 may be chip related components, and some of the chiprelated components may be a semiconductor device 1121. Meanwhile, theelectronic device is not necessarily limited to the smartphone 1100, butmay be other electronic devices.

Semiconductor Device (or Semiconductor Package)

Generally, numerous fine electrical circuits are integrated in asemiconductor chip. However, the semiconductor chip may not serve as asemiconductor finished product in oneself, and may be damaged due toexternal physical or chemical impact. Therefore, the semiconductor chipis not used in oneself, and is packaged and is used in an electronicdevice, or the like, in a package state.

The reason why semiconductor packaging is required is that there is adifference in a circuit width between the semiconductor chip and amainboard of the electronic device in terms of electrical connection. Indetail, a size of connection pads of the semiconductor chip and aninterval between the connection pads of the semiconductor chip are veryfine, but a size of component mounting pads of the mainboard used in theelectronic device and an interval between the component mounting pads ofthe mainboard are significantly larger than those of the semiconductorchip. Therefore, it may be difficult to directly mount the semiconductorchip on the mainboard, and packaging technology for buffering adifference in a circuit width between the semiconductor and themainboard is required.

A semiconductor device manufactured by the packaging technologydescribed above will hereinafter be described in more detail withreference to the drawings.

FIG. 3 is a schematic cross-sectional view illustrating a case in whicha three-dimensional (3D) ball grid array (BGA) package is mounted on amain board of an electronic device.

An application specific integrated circuit (ASIC) such as a graphicsprocessing unit (GPU) among semiconductor chips is very expensive, andit is thus very important to perform packaging on the ASIC at a highyield. For this purpose, a ball grid array (BGA) substrate 2210, or thelike, that may redistribute several thousands to several hundreds ofthousands of connection pads is prepared before a semiconductor chip ismounted, and the semiconductor chip that is expensive, such as a GPU2220, or the like, is mounted and packaged on the BGA substrate 2210 bysurface mounting technology (SMT), or the like, and is then mountedultimately on a main board 2110.

Meanwhile, in a case of the GPU 2220, it is required to significantlyreduce a signal path between the GPU 2220 and a memory such as a highbandwidth memory (HBM). To this end, a product in which a semiconductorchip such as the HBM 2240 is mounted and then packaged on an interposer2230, and is then stacked on a package in which the GPU 2220 is mounted,in a package-on-package (POP) form is used. However, in this case, athickness of a device is excessive increased, and there is a limitationin significantly reducing the signal path.

FIG. 4 is a schematic cross-sectional view illustrating a case in whicha 2.5D silicon interposer package is mounted on a main board.

As a method for solving the problem described above, it may beconsidered to manufacture a semiconductor device 2310 by 2.5D interposertechnology of surface-mounting and then packaging a first semiconductorchip such as a GPU 2220 and a second semiconductor chip such as an HBM2240 side-by-side with each other on a silicon interposer 2250. In thiscase, the GPU 2220 and the HBM 2240 having several thousands to severalhundreds of thousands of connection pads may be redistributed by thesilicon interposer 2250, and may be electrically connected to each otherat the shortest path. In addition, when the semiconductor device 2310 isagain mounted and redistributed on a BGA substrate 2210, or the like,the semiconductor device 2310 may be ultimately mounted on a main board2110. However, it is very difficult to form through-silicon vias (TSVs)in the silicon interposer 2250, and a cost required for manufacturingthe silicon interposer 2250 is significantly high, and the siliconinterposer 2250 is thus disadvantageous in increasing an area andreducing a cost.

FIG. 5 is a schematic cross-sectional view illustrating a case in whicha 2.5D organic interposer package is mounted on a main board.

As a method for solving the problem described above, it may beconsidered to use an organic interposer 2260 instead of the siliconinterposer 2250. For example, it may be considered to manufacture asemiconductor device 2320 by 2.5D interposer technology ofsurface-mounting and then packaging a first semiconductor chip such as aGPU 2220 and a second semiconductor chip such as an HBM 2240side-by-side with each other on the organic interposer 2260. In thiscase, the GPU 2220 and the HBM 2240 having several thousands to severalhundreds of thousands of connection pads may be redistributed by theorganic interposer 2260, and may be electrically connected to each otherat the shortest path. In addition, when the semiconductor device 2320 isagain mounted and redistributed on a BGA substrate 2210, or the like,the semiconductor device 2320 may be ultimately mounted on a main board2110. In addition, the organic interposer may be advantageous inincreasing an area and reducing a cost.

Meanwhile, such a semiconductor device 2320 is manufactured byperforming a package process of mounting chips 2220 and 2240 on theorganic interposer 2260 and then molding the chips. The reason is thatwhen a molding process is not performed, the semiconductor device is nothandled, such that the semiconductor device may not be connected to theBGA substrate 2210, or the like. Therefore, rigidity of thesemiconductor device is maintained by the molding. However, when themolding process is performed, warpage of the semiconductor device mayoccur, fillability of an underfill resin may be deteriorated, and acrack between a die and a molding material of the chips 2220 and 2240may occur, due to mismatch between coefficients of thermal expansion(CTEs) of the interposer 2260 and the molding material of the chips 2220and 2240, as described above.

Various exemplary embodiments in the present disclosure will hereinafterbe described in detail with reference to the accompanying drawings.

FIG. 6 is a schematic cross-sectional view illustrating a semiconductorpackage according to an exemplary embodiment in the present disclosure,and FIG. 7 is a plan view taken along line I-I′ of the semiconductorpackage of FIG. 6 .

Referring to FIGS. 6 and 7 , a semiconductor package 100A according tothe present exemplary embodiment may include a connection structure 120having a first surface 120A and a second surface 120B opposing eachother, first to third semiconductor chips 111, 112, and 113 disposed onthe first surface 120A of the connection structure 120, and anencapsulant 160 disposed on the first surface 120A of the connectionstructure 120 and encapsulating the first to third semiconductor chips111, 112, and 113.

The connection structure 120 may be used as an interposer packaging thesemiconductor chips in order to mount the semiconductor package 100A ona mainboard. The connection structure 120 may include a plurality ofinsulating layers 121, a plurality of redistribution layers 122 eachdisposed on the plurality of insulating layers 121, and a plurality ofconnection vias 123 penetrating through the plurality of insulatinglayers 121 and each connected to the plurality of redistribution layers122. A redistribution layer 122″ positioned on the first surface of theconnection structure among the plurality of redistribution layers 122may be provided as a connection wiring layer connected to each ofconnection pads 111P, 112P, and 113P of the first to third semiconductorchips 111, 112, and 113. A thickness of the redistribution layer 122″may be greater than that of each of the other redistribution layers 122.

The connection pads 111P, 112P, and 113P of the first to thirdsemiconductor chips 111, 112, and 113 may be electrically connected tothe connection redistribution layer 122″ of the plurality ofredistribution layers 122 using connection members 135, respectively.Each of the connection members 135 may be formed of a low melting pointmetal such as tin (Sn) or alloys including tin (Sn).

In addition, the semiconductor package 100A may include an underfillresin 170 disposed between surfaces (hereinafter, referred to as activesurfaces) of the first to third semiconductor chips 111, 112, and 113 onwhich the connection pads 111 p, 112 p, and 113 p are formed and thefirst surface 120A of the connection structure 120. The underfill resin170 may stably fix the first to third semiconductor chips 111, 112, and113 onto the connection structure 120. For example, the underfill resin170 may be a thermosetting resin such as epoxy, or the like.

The encapsulant 160 may be formed so that upper surfaces of the first tothird semiconductor chips 111, 112, and 113 are exposed through an uppersurface of the encapsulant 160. Heat may be easily dissipated throughthe exposed upper surfaces. The upper surfaces of the semiconductorchips 111, 112, and 113 and the upper surface of the encapsulant 160 maybe substantially coplanar with each other by a polishing process. Thesemiconductor package 100A is not limited thereto, and may be modifiedto have various forms in which a heat dissipation plate (see FIG. 11 )or another reinforcing member surrounding the semiconductor chips isadditionally introduced.

Underbump metallurgy (UBM) layers 145 may include UBM pads 142 disposedon the second surface 120B of the connection structure 120 and UBM vias143 connecting a redistribution layer 122′ adjacent to the secondsurface 120B of the connection structure 120 among the plurality ofredistribution layers 122 and the UBM pads 142 to each other.

FIG. 8 is an enlarged cross-sectional view of portion “A” of thesemiconductor package of FIG. 6 .

Referring to FIGS. 6 and 8 , the plurality of connection vias 123 usedin the present exemplary embodiment may have different formationdirections in relation to one intermediate redistribution layer 122P(hereinafter, referred to as an “intermediate redistribution layer122P”). In detail, connection vias 123″ adjacent to the first surface120A among the plurality of connection vias 123 may have a taperedstructure in which they become narrow toward the second surface 120B,while the other connection vias 123′ of the plurality of connection vias123 may have a tapered structure in which they become narrow toward thefirst surface 120A. In other words, the connection vias 123″ adjacent tothe first surface 120A may be represented as having a lower diameter (ora lower width) d_(a) smaller than an upper diameter (or an upper width)d_(b), while the other connection vias 123′ may be represented as havinga lower diameter (or a lower width) d₁ greater than an upper diameter(or an upper width) dz.

In addition, the UBM vias 143 may also have a tapered structure in whichthey become narrow toward the first surface 120A, similar to the otherconnection vias 123′.

The connection vias 123″ that become narrow toward the second surface120B may be the uppermost connection vias connected to a connectionredistribution layer 122″, and a case in which connection vias 123″ ofonly one layer are tapered in the same direction is exemplified, butconnection vias of two or more layers adjacent to the first surface 120Amay have a tapered structure so that they become narrow toward thesecond surface 120B. However, in order to sufficiently alleviateundulation, the connection vias 123″ tapered to become toward the secondsurface 120B may be designed to have layers that are the same as or lessthan those of the other connection vias 123′.

The different formation directions of the connection vias 123′ and 123″may be implemented by introducing a transfer process using an additionalcarrier substrate in a build-up process of the redistribution layers 122(see FIGS. 9A through 9F). In a build-up process of a primaryredistribution layer performed before a resultant is transferred to theadditional carrier substrate, the UBM pad 142 may be disposed on theuppermost level, and an undulation problem may thus be significantlyalleviated as compared to a case in which the UBM pad 142 is positionedon a level below a build-up structure. In addition, since each of theplurality of insulating layers 121 includes an organic material, an theundulation problem may occur when the UBM pad 142 is positioned on alevel below the redistribution layer 122 in the build-up process, and asillustrated in FIG. 8 , a thickness t₀ of the UBM pad 142 may be greaterthan a thickness ti of the redistribution layer 122. Therefore, such aproblem may more seriously occur. However, a structure according to thepresent exemplary embodiment may be understood as a resultant of aprocess (that is, a process of forming the UBM pad 142 on the uppermostlevel in an initial build-up process) of significantly alleviating suchan undulation problem.

In the present exemplary embodiment, a diameter (or a width) d₀ of alower portion of the UBM via 143 may be greater than a diameter (or awidth) d₁ of each lower portion of the plurality of connection vias 123.However, the diameter (or the width) d₀ of the lower portion of the UBMvia 143 is not limited thereto. In some exemplary embodiment, eventhough the diameter (or the width) d₀ of the lower portion of the UBMvia 143 is not greater than the diameter (or the width) d₁ of each lowerportion of the plurality of connection vias 122, and is the same orsmaller than the diameter (or the width) d₁ of each lower portion of theplurality of connection vias 122, a plurality of UBM vias associatedwith one UBM pad may be formed.

The UBM pad 142 used in the present exemplary embodiment may have anintegrated structure with the UBM via 143. The redistribution layer 122″positioned on the first surface 120A of the connection structure 120 mayhave an integrated structure with a connection via 123″ adjacentthereto.

In the present specification, a term “integrated structure” does notmean that two components are simply in contact with each other, andrefers to a structure in which two components are formed integrally witheach other using the same material by the same process. For example,when a pattern (a redistribution layer or a pad) and a via are formedtogether by the same plating process, the via and the pattern may becalled the integrated structure.

The semiconductor package 100A according to the present exemplaryembodiment may include a passivation layer 141 disposed on the secondsurface 120B of the connection structure 120 and embedding at leastportions of the UBM pads 142.

The passivation layer 141 may surround side surfaces of the UBM pads 142so that one surfaces of the UBM pads 142 are exposed. In anotherexemplary embodiment, the passivation layer 141 may be formed so thatside surfaces of the UBM pad 142 adjacent to the exposed one surfaces ofthe UBM pads 142 are also partially exposed (see FIG. 11 ). Thepassivation layer 141 may protect the connection structure 120 fromexternal physical or chemical damage.

The respective components included in the semiconductor package 100Aaccording to the present exemplary embodiment will hereinafter bedescribed in more detail.

The connection structure 120 may redistribute the respective connectionpads 111P, 112P, and 113P of the first to third semiconductor chips 111,112, and 113. Several thousands to several hundreds of thousands ofconnection pads 111P, 112P, and 113P of the first to third semiconductorchips 111, 112, and 113 having various functions may be redistributed bythe connection structure 120, and may be physically or electricallyexternally connected through electrical connection metals 150 dependingon functions. In addition, the respective connection pads 111P, 112P,and 113P of the first to third semiconductor chips 111, 112, and 113 maybe electrically connected to each other at the shortest path through theconnection structure 120. The connection structure 120 may include theplurality of insulating layers 121, the redistribution layers 122 formedon or in the plurality of insulating layers 121, and the connection vias123 penetrating through the insulating layers 121 and electricallyconnecting the redistribution layers 122 formed on different layers toeach other. The number of layers of the connection structure 120 may bemore than that illustrated in the drawings or be less than thatillustrated in the drawings. The connection structure 120 having such aform may be used as a 2.5D type organic interposer.

The plurality of insulating layers 121 may serve as dielectric layers ofthe connection structure 120, and a material of each of the insulatinglayers 121 may be a thermosetting resin such as an epoxy resin, athermoplastic resin such as a polyimide resin, a resin in which thethermosetting resin or the thermoplastic resin is mixed with aninorganic filler, for example, an organic insulating material such asAjinomoto Build-up Film (ABF). In some exemplary embodiments, a resin inwhich a thermosetting resin or a thermoplastic resin is impregnatedtogether with an inorganic filler in a core material such as a glassfiber (or a glass cloth or a glass fabric), for example, prepreg, or thelike, may also be used as the material of each of the insulating layers121.

In some exemplary embodiments, a photosensitive insulating material suchas a photoimagable dielectric (PID) resin may be used as the material ofeach of the insulating layers 121. Since the plurality of insulatinglayers 121 may be integrated with each other depending on a process asin the present exemplary embodiment, a boundary between the insulatinglayers 121 may be not apparent. Since the plurality of insulating layers121 each include the organic material, the plurality of insulatinglayers 121 may be exposed to an undulation problem. The plurality ofinsulating layers 121 used in the present exemplary embodiment may beformed using the same insulating material.

A material of the passivation layer 141 is not particularly limited, andmay be, for example, the insulating material of the plurality ofinsulating layers 121 described above. In some exemplary embodiments,the material of the passivation layer 141 may be different from that ofthe plurality of insulating layers 121. For example, the passivationlayer 141 may include an ABF, and the plurality of insulating layers 121may be formed of a PID.

The plurality of redistribution layers 122 may redistribute theconnection pads 111P, 112P, and 113P, and serve to connect theconnection pads 111P, 112P, and 113P to each other depending on asignal, power, or the like. Each of the redistribution layers 122 mayinclude, for example, a conductive material such as copper (Cu),aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb),titanium (Ti), or alloys thereof. The redistribution layers 122 mayperform various functions depending on designs of corresponding layers.For example, the redistribution layers 122 may include ground (GND)patterns, power (PWR) patterns, signal (S) patterns, and the like. Here,the signal (S) patterns may include various signals except for theground (GND) patterns, the power (PWR) patterns, and the like, such asdata signals, and the like. In addition, the redistribution layers 122may include via pads, electrical connection metal pads, and the like. Asurface treatment layer P may be formed on surfaces of patterns of theredistribution layer 122 serving as pads for mounting the first to thirdsemiconductor chips 111, 112, and 113. The surface treatment layer P isnot particularly limited as long as it is known in the related art, andmay be formed by, for example, electrolytic gold plating, electrolessgold plating, organic solderability preservative (OSP) or electrolesstin plating, electroless silver plating, electroless nickelplating/substituted gold plating, direct immersion gold (DIG) plating,hot air solder leveling (HASL), or the like, but is not limited thereto.

The plurality of connection vias 123 may electrically connect theredistribution layers 122 formed on different layers to each other,resulting in an electrical path in the connection structure 120. Each ofthe connection vias 123 may include, for example, a conductive materialsuch as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au),nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The connectionvias 123 may be completely filled with a conductive material, but arenot limited thereto. The plurality of connection vias 123 may havestructures tapered in different directions, as described above, and across-sectional shape of each of the plurality of connection vias 123may be understood to be a substantially trapezoidal or inversetrapezoidal shape in FIGS. 6 and 8 .

Each of the first to third semiconductor chips 111, 112, and 113 may bean integrated circuit (IC) provided in an amount of several hundreds toseveral millions of elements or more integrated in a single chip. Inthis case, a base material of a body of each of the first to thirdsemiconductor chips may be silicon (Si), germanium (Ge), galliumarsenide (GaAs), or the like. Various circuits may be formed on each ofthe bodies. For example, each of the connection pads 111P, 112P, and113P may be formed of a conductive material such as aluminum (Al), orthe like. Passivation layers exposing the connection pads 111P, 112P,and 113P may be formed on the respective bodies, and may be oxidelayers, nitride layers, or the like, or double layers of an oxide layerand a nitride layer. An insulating layer, and the like, may further bedisposed in required positions. In some exemplary embodiments, thesemiconductor package may further include a redistribution layer (notillustrated) formed at a wafer level on active surfaces of the first tothird semiconductor chips 111, 112, and 113. In addition, the first tothird semiconductor chips 111, 112, and 113 may have bumps 111B, 112B,and 113B each connected to the connection pads 111P, 112P, and 113P,respectively. Each of the bumps 111B, 112B, and 113B may be formed of ametal or a solder. The first to third semiconductor chips 111, 112, and113 may be connected to an exposed upper redistribution layer 122″ ofthe connection structure 120 through the connection pads 111P, 112P, and113P and/or the bumps 111B, 112B, and 113B, and connection members 135such as solders, or the like. Each of the first to third semiconductorchips 111, 112, and 113 may be fixed to the connection structure 120 bythe underfill resin 170, as described above.

In some exemplary embodiment, the first semiconductor chip 111 may be anASIC such as a GPU. A plurality of second and third semiconductor chips112 and 113 (a case in which the numbers of each of second and thirdsemiconductor chips 112 and 113 is two is exemplified) may be memoriessuch as HBMs. That is, each of the first to third semiconductor chips111, 112, and 113 may be an expensive chip having several hundreds ofthousands or more of inputs/outputs (I/Os), but is not limited thereto.For example, the two second semiconductor chips 112, the HBMs may bedisposed side-by-side with each other at one side of the firstsemiconductor chip 111, the ASIC such as the GPU, or the like, and thetwo third semiconductor chips 113, the HBMs may be disposed side-by-sidewith each other at the other side of the first semiconductor chip 111,the ASIC such as the GPU, or the like. A combination of thesemiconductor chips that may be used in the present exemplary embodimentis not limited thereto, and may include at least one selected amongvarious logic elements and various memory elements, and the number ofthe semiconductor chips may be appropriately selected.

The underbump metallurgy (UBM) layers 145 may improve connectionreliability of the electrical connection metals 150, resulting inimprovement of reliability of the semiconductor package 100A. The UBMlayers 145 may be formed in the openings of the passivation layer 141,and may be electrically connected to the redistribution layer 122 of theconnection structure 120. The UBM layers 145 may be formed by any knownmetallization method. For example, each of the UBM layers 145 mayinclude a metal such as copper (Cu).

The electrical connection metals 150 may physically or electricallyexternally connect the semiconductor package 100A. For example, thesemiconductor package 100A may be mounted on the BGA substrate throughthe electrical connection metals 150. Each of the electrical connectionmetals 150 may be formed of a conductive material and a low meltingpoint metal such as tin (Sn) or alloys including tin (Sn). In moredetail, each of the electrical connection metals 150 may be formed of asolder, or the like. Each of the electrical connection metals 150 may bea land, a ball, a pin, or the like. The electrical connection metals 150may be formed as a multilayer or single layer structure. When theelectrical connection metals 150 are formed as a multilayer structure,the electrical connection metals 150 may include a copper (Cu) pillarand a solder. When the electrical connection metals 150 are formed as asingle layer structure, the electrical connection metals 150 may includea tin-silver solder or copper (Cu). However, this is only an example,and the electrical connection metals 150 are not limited thereto. Thenumber, an interval, a disposition form, and the like, of electricalconnection metals 150 are not particularly limited, but may besufficiently modified depending on design particulars by those skilledin the art. For example, the electrical connection metals 150 may beprovided in an amount of several thousands to several hundreds ofthousands according to the number of connection pads 111P, 112P, and113P, or may be provided in an amount of several thousands to severalhundreds of thousands or more or several thousands to several hundredsof thousands or less.

An example of a method of manufacturing a semiconductor packageaccording to the present exemplary embodiment will hereinafter bedescribed in detail. A method of manufacturing the semiconductor package100A illustrated in FIG. 6 will be divided into and described asprocesses (FIGS. 9A through 9F) of forming the connection structure andprocesses (FIGS. 10A through 10C) of manufacturing the semiconductorpackage.

FIGS. 9A through 9F are cross-sectional views for describing mainprocesses of forming the connection structure in a method ofmanufacturing the semiconductor package according to an exemplaryembodiment in the present disclosure.

Referring to FIG. 9A, a first carrier substrate 210 for forming theconnection structure may be prepared.

The first carrier substrate 210 may include a core layer 211 and metallayers 212 respectively formed on opposite surfaces of the core layer.The core layer 211 may be formed of an insulating resin or an insulatingresin (for example, prepreg) including an inorganic filler and/or aglass fiber, and the metal layers 212 may be metal layers formed ofcopper (Cu). The first carrier substrate 210 may include a release layer213 formed on one surface thereof. Such a structure of the first carriersubstrate and the use of the release layer may be variously modified.

Then, referring to FIG. 9B, an insulating layer 121 and an intermediateredistribution layer 122P may be formed on the first carrier substrate210.

The intermediate redistribution layer 122P may be provided as a patternwithout including connection vias integrated therewith. In the presentprocess, one insulating layer 121 may be formed on the release layer213, the intermediate redistribution layer 122P may be formed on the oneinsulating layer 121 without including the connection vias, and anotherinsulating layer 121 may then be formed to cover the intermediateredistribution layer 122P. The intermediate redistribution layer 122Pformed in the present process may be one of the plurality ofredistribution layers 122, and connection vias 123′ disposed above andbelow the intermediate redistribution layer 122P may have differentformation directions. The insulating layer 121 may be formed bylaminating a film form or applying and hardening a liquid phase form.

Then, referring to FIG. 9C, the redistribution layer 122′ and theconnection vias 123′ connected to the intermediate redistribution layer122P may be formed.

In the present process, the redistribution layer 122′ may be formedtogether with the connection vias 123′ by forming holes connected to theintermediate redistribution layer 122P in the insulating layer 121,forming a dry film having a desired pattern, and performing a platingprocess using the dry film. When the insulating layer 121 is formed of aPID, the holes of the insulating layer 121 may be formed by aphotolithography process, and a hole array of a fine pitch may beimplemented.

Then, referring to FIG. 9D, a process of forming the insulating layer121 and a process of forming the connection vias 123′ and theredistribution layer 122′ may be repeatedly performed, and the UBMlayers 145 may be formed on an insulating layer 121 positioned at anupper portion of the connection structure.

Similar to the process described with reference to FIG. 9C, the processof forming the insulating layer 121 and the process of forming theconnection vias 123′ and the redistribution layer 122′ may be repeatedlyperformed as many times as necessary. The UBM pads 142 and the UBM vias143 connected to a redistribution layer 122′ adjacent thereto may beformed on and in the insulating layer 121 positioned at the upperportion of the connection structure to form desired UBM layers 145.

A process of forming the UBM layers 145 may be performed continuously inthe same line as that of the process of forming the connection vias 123′and the redistribution layer 122′. The connection vias 123′ and theredistribution layer 122′, and the UBM vias 143 and the UBM pads 142formed by the same plating process may be formed to have integratedstructures, respectively.

Meanwhile, the UBM pad 142 may have a thickness greater than that of theredistribution layer 122′, as described above. For example, thethickness of the UBM pad 142 may be three times or more the thickness ofthe redistribution layer 122′. In a case in which the UBM pads 142 thatare relatively thick are introduced and positioned at a lower portion ofthe connection structure before a process of forming a series ofredistribution layers 122′ as illustrated in FIGS. 9C and 9D, as thenumber of layers is increased, an undulation problem may severely occur.However, the UBM pads 142 may be disposed on the uppermost level in anoverall build-up process as illustrated in FIG. 9D, and thus, theundulation problem may be significantly reduced.

Then, referring to FIG. 9E, the passivation layer 141 may be formed inthe vicinity of the UBM pads 142, and a second carrier substrate 220 maybe attached to the passivation layer 141.

In a case in which the passivation layer 141 is formed to cover the UBMpads 142, a Descum or etching process may be applied in the subsequentprocess to expose the UBM pads 142. However, in the present process, thepassivation layer 141 may be formed to surround side surfaces of the UBMpads 142 while have one surfaces of the UBM pads 142 exposed from thepassivation layer 141. In this case, a Descum or etching process usingplasma, or the like, for exposing the UBM pads 142 may be omitted in thesubsequent process, but the present process is not limited thereto. Thesecond carrier substrate 220 may include a release layer 223 formed on abonded surface, similar to the first carrier substrate 210, but is notlimited thereto.

Then, referring to FIG. 9F, the first carrier substrate 210 may beremoved, and additional connection vias 123″ and redistribution layer122″ may then be formed on an exposed insulating layer 121.

Since the connection vias 123″ connected to the redistribution layer122″ formed in the present process are formed after a resultant istransferred to the second carrier substrate 220, a formation directionof the connection vias 123″ may be opposite to that of the connectionvias 123′ connected to the redistribution layer 122′ formed before thetransfer process. The connection vias 123″ formed in the present processmay have a tapered structure in which they become narrow toward thesecond carrier substrate 220 (or the intermediate redistribution layer122P), while the other connection vias 123′ formed before the presentprocess may have a tapered structure in which they become narrow towardthe intermediate redistribution layer 122P.

In the present exemplary embodiment, after the resultant is transferredto the second carrier substrate 220, the redistribution layer 122″formed on an exposed surface of the insulating layer 121 may be aconnection redistribution layer that is to be connected to theconnection pads of the semiconductor chip. Here, a form in which oneredistribution layer 122″ is formed after the transfer process isexemplified, but in some exemplary embodiments, two or moreredistribution layers and connection vias may be formed in the presentprocess.

FIGS. 10A through 10C illustrate processes of manufacturing thesemiconductor package using the connection structure illustrated in FIG.9F as portions of the method of manufacturing the semiconductor packageaccording to an exemplary embodiment in the present disclosure.

Referring to FIG. 10A, the first to third semiconductor chips 111, 112,and 113 may be mounted on the connection structure 120.

The present mounting process may be performed using connection members135, such as solders, or the like. Additionally, the semiconductor chips111, 112, and 113 may be more stably fixed by the underfill resin 170.Then, the encapsulant 160 encapsulating the semiconductor chips 111,112,and 113 may be formed on the connection structure 120. The encapsulant160 may be formed by laminating a film form or applying and hardening aliquid phase form.

Then, referring to FIG. 10B, the encapsulant 160 may be grinded so thatsurfaces of the first to third semiconductor chips 111, 112, and 113 areexposed.

Upper surfaces of the first to third semiconductor chips 111, 112, and113 may be disposed on the same level by the present grinding process,and may be substantially coplanar with an upper surface of theencapsulant. Since portions of the semiconductor chips partially removedin the grinding process are inactive regions, they may not be related tofunctions, and the semiconductor chips are exposed externally of theencapsulant, and a heat dissipation effect may thus be improved.

Then, referring to FIG. 10C, the second carrier substrate 220 may beremoved from the connection structure 120, and the electrical connectionmetals 150 may be formed on the exposed UBM layers 145.

After the second carrier substrate 220 is removed and before theelectrical connection metals 150 are formed, portions of the passivationlayer 141 may be removed by a Descum or etching process to allow the UBMpads 142 to protrude from the remaining surface of the passivation layer(see FIG. 11 ).

The series of processes described above may be performed using a panelstructure having a large area, and when a dicing process is performedafter the series of processes are completed, a plurality ofsemiconductor packages 100A may be manufactured by performing theprocess once.

FIG. 11 is a schematic cross-sectional view illustrating a semiconductorpackage according to another exemplary embodiment in the presentdisclosure, and FIG. 12 is a plan view taken along line II-IF of thesemiconductor package of FIG. 11 .

Referring to FIGS. 11 and 12 , it may be understood that a semiconductorpackage 100B according to the present exemplary embodiment has astructure similar to that illustrated in FIGS. 6 through 8 except thatdifferent numbers of (two) redistribution layers are formed after atransfer process, another array of semiconductor chips and a heatdissipation plate are additionally used, and portions of side surfacesof UBM pads are exposed. Components according to the present exemplaryembodiments may be understood with reference to the description for thesame or similar components of the semiconductor package 100A illustratedin FIGS. 6 through 8 unless explicitly described otherwise.

In the semiconductor package 100B according to the present exemplaryembodiment, a plurality of connection vias 123 used in the presentexemplary embodiment may have different formation directions in relationto an intermediate redistribution layer 122P. In detail, two connectionvias 123″ adjacent to a first surface 120A among the plurality ofconnection vias 123 may have a tapered structure in which they becomenarrow toward a second surface 120B, while the other two connection vias123′ and UBM vias 143 may have a tapered structure in which they becomenarrow toward the first surface 120A. The connection vias 123″ formedafter the transfer process, that is, the connection vias 123″ adjacentto the first surface 120A and having a different formation direction maybe designed in various amounts corresponding to some of all theconnection vias 123.

As illustrated in FIGS. 11 and 12 , the semiconductor package 100Baccording to the present exemplary embodiment may include two secondsemiconductor chips 112 disposed at one side of one first semiconductorchip 111 unlike the previous exemplary embodiment. As described above,various kinds and numbers of semiconductor chips may be arranged on theconnection structure 120.

A thermally conductive material layer 191 may be disposed between a heatdissipation plate 195 and the first and second semiconductor chips 111and 112, and may be in contact with upper surfaces of the first andsecond semiconductor chips 111 and 112. The thermally conductivematerial layer 191 may help heat generated from the first and secondsemiconductor chips 111 and 112 to be smoothly dissipated to the heatdissipation plate 195. The thermally conductive material layer 191 maybe formed of a thermal interface material (TIM). For example, thethermally conductive material layer 191 may be formed of an insulatingmaterial or be formed of a material that may include the insulatingmaterial to maintain an electrical insulating property. The thermallyconductive material layer 191 may include, for example, an epoxy resin.

The heat dissipation plate 195 may be disposed on the thermallyconductive material layer 191. The heat dissipation plate 195 may be,for example, a heat sink, a heat spreader, a heat pipe, or a liquidcooled cold plate.

In the present exemplary embodiment, a passivation layer 141 maypartially surround side surfaces of the UBM pads 142 so that onesurfaces of the UBM pads 142 and portions e of the side surfaces of theUBM pads 142 adjacent to the one surfaces of the UBM pads 142 areexposed. As described above, portions of the passivation layer 141 maybe removed by a Descum or etching process to allow the UBM pads 142 toprotrude from the remaining surface of the passivation layer 141.

As set forth above, according to an exemplary embodiment in the presentdisclosure, a transfer process using an additional carrier substrate maybe introduced in a build-up process of the redistribution layers, suchthat an undulation problem due to the UBM layers may be significantlyreduced, and the connection vias may have different formation directionsin an ultimate structure. In addition, a critical dimension of a finecircuit may be satisfied by removing the undulation. In some exemplaryembodiments, an additional process for exposing the UBM pads may beomitted.

While exemplary embodiments have been shown and described above, it willbe apparent to those skilled in the art that modifications andvariations could be made without departing from the scope of the presentinvention as defined by the appended claims.

What is claimed is:
 1. A method of manufacturing a semiconductorpackage, the method comprising: forming a base insulating layer on afirst carrier substrate; forming a planar conductive pattern on the baseinsulating layer; forming a redistribution structure on the baseinsulating layer, wherein the redistribution structure includes aplurality of insulating layers, and a plurality of redistribution layersbetween the plurality of insulating layers, respectively, each of theplurality of redistribution layers having a conductive via connected toan adjacent one of planar conductive pattern and the plurality ofredistribution layers; forming an underbump metallurgy (UBM) pad on anupper surface of the redistribution structure, the UBM pad having a UBMvia connected to an uppermost redistribution layer among the pluralityof redistribution layers; attaching a second carrier substrate to theupper surface of the redistribution structure, on which the UBM pad isformed, so that the redistribution structure is provided between thefirst carrier substrate and the second carrier substrate; removing thefirst carrier substrate from the base insulating layer; and forming aconnection pad on the base insulating layer, the connection pad having aconnection via penetrating through the base insulating layer andconnected to the planar conductive pattern.
 2. The method of claim 1,wherein the UBM pad has a thickness greater than that of each of theplurality of redistribution layers.
 3. The method of claim 1, whereinthe connection via has a tapered structure narrowed toward a firstdirection, and each of the conductive via and the UBM via has a taperedstructure narrowed toward a second direction opposed to the firstdirection.
 4. The method of claim 1, further comprising, after theforming the connection pad, disposing at least one semiconductor chip onthe base insulating layer to electrically connected to the connectionpad.
 5. The method of claim 4, further comprising, forming anencapsulant encapsulating the at least one semiconductor chip andgrinding the encapsulant to expose an upper surface of the at least onesemiconductor chip.
 6. The method of claim 1, further comprising, beforethe attaching the second carrier substrate, forming a passivation layeron the upper surface of the redistribution structure to cover the UBMpad.
 7. The method of claim 6, further comprising removing the secondcarrier substrate from the passivation layer, and exposing at least aportion of a side surface of the UBM pad from the passivation layer. 8.The method of claim 6, wherein the passivation layer includes a materialdifferent from that of each of the plurality of insulating layers. 9.The method of claim 6, wherein the passivation layer includes a samematerial as that of each of the plurality of insulating layers.
 10. Themethod of claim 9, wherein the passivation layer and the plurality ofinsulating layers include a photoimagable dielectric (PID).
 11. Themethod of claim 1, wherein the UBM via has a width greater than that ofthe conductive via.
 12. The method of claim 1, wherein each of theplurality of redistribution layers is formed along with the conductivevia by a same process.
 13. The method of claim 1, wherein the UBM pad isformed along with the UBM via by a same process.
 14. The method of claim1, further comprising removing the second carrier substrate.
 15. Amethod of manufacturing a semiconductor package, the method comprising:forming a planar conductive pattern on a first carrier substrate;forming a redistribution structure on the first carrier substrate,wherein the redistribution structure includes a plurality of firstinsulating layers, and a plurality of redistribution layers between theplurality of first insulating layers, respectively, each of theplurality of redistribution layers having a conductive via connected toan adjacent one of planar conductive pattern and the plurality ofredistribution layers; forming an underbump metallurgy (UBM) pad on anupper surface of the redistribution structure, the UBM pad having a UBMvia connected to an uppermost redistribution layer among the pluralityof redistribution layers; attaching a second carrier substrate to theupper surface of the redistribution structure, on which the UBM pad isformed, so that the redistribution structure is provided between thefirst carrier substrate and the second carrier substrate; removing thefirst carrier substrate from a lower surface of the redistributionstructure, on which the planar conductive pattern is formed; forming asecond insulating layer on the lower surface of the redistributionstructure to cover the planar conductive pattern; forming a connectionpad on the second insulating layer, the connection pad having aconnection via penetrating through the second insulating layer andconnected to the planar conductive pattern; and disposing at least onesemiconductor chip on the second insulating layer to electricallyconnected to the connection pad.
 16. The method of claim 15, wherein theUBM pad has a thickness greater than that of each of the plurality ofredistribution layers, and the connection via has a tapered structurenarrowed toward a first direction, and each of the conductive via andthe UBM via has a tapered structure narrowed toward a second directionopposed to the first direction.
 17. A method of manufacturing asemiconductor package, the method comprising: forming a planarconductive pattern on a first carrier substrate; forming a firstredistribution structure on the first carrier substrate, wherein thefirst redistribution structure includes a plurality of first insulatinglayers, and a plurality of first redistribution layers between theplurality of first insulating layers, respectively, each of theplurality of first redistribution layers having a first conductive viaconnected to an adjacent one of planar conductive pattern and theplurality of first redistribution layers; forming an underbumpmetallurgy (UBM) pad on an upper surface of the first redistributionstructure, the UBM pad having a UBM via connected to an uppermostredistribution layer among the plurality of first redistribution layers;attaching a second carrier substrate to the upper surface of the firstredistribution structure, on which the UBM pad is formed, so that thefirst redistribution structure is provided between the first carriersubstrate and the second carrier substrate; removing the first carriersubstrate from a lower surface of the first redistribution structure, onwhich the planar conductive pattern is formed; forming a secondredistribution structure on the lower surface of the firstredistribution structure, wherein the second redistribution structureincludes at least one second insulating layer and at least one secondredistribution layer, the at least one second redistribution layerhaving a second conductive via connected to the planar conductivepattern; forming a connection pad on the second redistributionstructure, the connection pad having a connection via penetratingthrough the at least one second insulating layer and connected to the atleast one second redistribution layer; and disposing at least onesemiconductor chip on the at least one second insulating layer toelectrically connected to the connection pad.
 18. The method of claim17, wherein a number of the at least one second redistribution layer issmaller than a number of the plurality of first redistribution layers.19. The method of claim 18, wherein the plurality of first insulatinglayers and the at least one second insulating layer include aphotoimagable dielectric (PID).
 20. The method of claim 17, wherein eachof the connection via and the second conductive via has a taperedstructure narrowed toward a first direction, and each of the firstconductive via and the UBM via has a tapered structure narrowed toward asecond direction opposed to the first direction.